Semiconductor memory device.

摘要

A semiconductor memory device (1) having data buses (51-58) for connecting memory cells in a plurality of memory cell arrays (11-18) having repetitive patterns with input/output buffer circuits (61-68) includes a plurality of column decoders (31-34) adjacent the memory cell arrays and having repetitive patterns. A portion (Y₀) of each of the column decoders (31-34) is displaced from the remainder to a separate location on a substrate to leave a blank portion in each column decoder (31-34). The data buses (51-58) pass through the blank portions, along with conductors (421-426) for connecting the displaced portions (Y₀) of the column decoders (31-34) to their corresponding memory cell arrays (11-18).