| 摘要 |
The invention relates to a clock signal regenerator arrangement 1 shown in Figure 1. …<??>The clock signal regenerator arrangement 1 comprises two PLL circuits 2-1 and 2-2 respectively, producing regenerated clock signals c and r respectively and high-frequency oscillator signals a and q respectively, two time window signal generators 8,9, each connected to a respective one of the PLL circuits 2-1,2-2, and also a logic circuit 7 connected to the time window signal generators 8,9. …<??>The clock signal regenerator arrangement 1 has for its object the regeneration of a clock signal which has a very high degree of accuracy as regards its frequency and phase. …<??>To that end, time window signals g, u whose relative position is a measure of the phase difference between the regenerated clock signals c, r and whose widths depend on the period durations of the oscillator signals a and q respectively are generated in the time window signal generators 8 and 9 respectively. In the logic circuit 7 the time window signals clock the clock signal c, which is only conveyed to the output terminal 19 of the clock signal regenerator arrangement 1 if the phase difference is less than half the period duration of the oscillator signals a and q. |
