| 摘要 |
<p>A complementary semiconductor memory device comprises a memory cell array (73; 100) in which each cell (MCp; MCpo) has a first MIS transistor (Qp; Qp1, Qp2) of a first conduction type connected to a word line, a decoding circuit (71) for decoding an input address signal and generating a selecting signal, and a driving circuit (72; 90) having a second MIS transistor (Q80) of a second conduction type opposite to the first conduction type for driving the word line, thereby improving the operation speed thereof, while decreasing the possibility of the destruction of information in each cell by alpha -rays.</p> |
