SENSE AMPLIFIER SYSTEM FOR SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE:To reduce an occupying space on a chip without reducing the speed of high speed read operation by providing a latching circuit which latches the output of a sense amplifier and using the latching circuit in common by the sense amplifier of plural columns. CONSTITUTION:The first bit lines (BL11 and -BL11) - (BL42 and -BL42) are used with columns in common and a latching circuit LA11 and a switching circuit S11-S42 are controlled by the outputs of a column system and a row system so as to connect the latching circuit LA11 to sense amplifiers SA11-SA42 selectively. The second bit lines (2BL1 and -2BL1) are used with adjacent two pairs of columns in common and switching circuits 2S11 and 2S21 which are switch-controlled selectively are provided between each latching circuit LA11 and LA21 and the second bit lines. The second bit lines are connected to data lines DL and the inverse of DL through a switch 2S1 that is controlled by the decoder output of the column system and the data lines DL and the inverse of DL are connected to an input circuit Din and an output circuit Dout.