| 摘要 |
PURPOSE:To obtain a phase comparison circuit with a simple circuit constitution by using an AND output between an FF output set by a ground frame timing pulse and reset by a pulse obtained from the count of the same frame counter and the 2nd external setting value and a satellite frame timing pulse. CONSTITUTION:A synchronizing pulse added by a ground frame counter 6 is counted by a reference CP, a frame synchronizing pulse corresponding to the 1st external setting value is generated (7), delayed by a phase at an FF 10 to set an FF 9-2, an external setting value M is added to a decoder 9-1 to set a phase lag permissible range, the FF 9-2 is reset at the location of the setting value M and an 'L' output is fed to an AND circuit 9-3 by the permissible range. Even when an asynchronous satellite frame synchronizing pulse of 'H' level is fed, no output is given to discriminate that the asynchronous satellite frame synchronizing pulse shifted by the Doppler effect is within the permissible range and since it can be used a1 it is, the phase comparator circuit is simplified. |
