Clock signal test circuit

摘要

An integrated circuit which has serially connected clock drivers for generating sequential clock signals further includes test circuitry for testing for the occurence of the clock signals. The test circuitry includes a current source for each of the sequential clock signals each of which is enabled upon receiving its associated clock signal. Consequently, the current sources are sequentially enabled until a clock signal fails to occur at which time no more clock signals occur so that no more current sources are enabled. The current sources are connected to a probe pad which is accessible external to the integrated circuit. Test apparatus for detecting the enabled current sources can be connected to the integrated circuit at the probe pad.