发明名称 Asynchronous data bus system
摘要 An active data bus includes a plurality of multiplex terminals serially interconnected to form a closed loop. Each terminal is capable of assuming either a relay configuration wherein data received from a preceding terminal are retransmitted to a succeeding terminal or a transmit access configuration wherein the loop is opened at the terminal and locally-generated data are introduced therein. Each terminal is capable of functioning either in a diagnostic mode whereby system access is obtained by programmed action of the terminal's control microprocessor or in a user access mode whereby access is obtained without microprocessor action by virtue of hardware "capturing" an access window bit introduced by the last-accessing terminal. The last-accessing terminal functions to close the loop after introducing its data and before the access window has completely traversed the system. The access window is thereupon "trapped" on the closed loop and circulates until it is "captured" by the next accessing terminal. The data bus includes redundant data paths between terminals. The terminal control microprocessors are each capable of selecting either of two receiving paths and two transmitting paths to form the closed loop. The programs of the terminal control microprocessors include cooperative diagnostic controller and diagnostic follower algorithms. The plurality of microprocessors intercommunicate synchronously via the diagnostic mode to construct an optimum data loop from available system resources. Subsequently the member terminals collectively switch to the user access mode to asynchronously transfer data generated by user data sources directed to user data sinks.
申请公布号 US4627070(A) 申请公布日期 1986.12.02
申请号 US19810302939 申请日期 1981.09.16
申请人 FMC CORPORATION 发明人 CHAMPLIN, KEITH S.;PREIMESBERGER, ERNEST C.;MILLER, GEORGE W.
分类号 H04L12/433;H04L12/437;(IPC1-7):H04Q3/00;H04J3/06 主分类号 H04L12/433
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