发明名称 MEMORY CONTROL SYSTEM
摘要 PURPOSE:To process easily image data with simple constitution by attaining the simultaneous access to plural bits in the horizontal and vertical directions as well as the 45 deg. direction from an optional address on a 2-dimensional space. CONSTITUTION:A chip selection control circuit 2 for selection of chips and an address qualifying circuit 3 for qualification of addresses are provided to a memory array 1 containing (WXW) pieces of memories. The circuit 3 gives accesses with prescribed bit qualification to addresses of horizontal and vertical directions when the circuit 3 exceeds the boundary of W bits to which the simultaneous access is possible.
申请公布号 JPS61202248(A) 申请公布日期 1986.09.08
申请号 JP19850044086 申请日期 1985.03.06
申请人 FUJITSU LTD 发明人 OKA YASUKATSU
分类号 G06F12/00;G06F12/06;G06T1/60;G11C7/00 主分类号 G06F12/00
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