Integrable demodulator for digital signals on a carrier, and use thereof

摘要

The signal to be demodulated (input signal) passes to a first binary counter (Z). This counter thereupon begins to count, latches itself by means of a logic circuit (V) and reveals this time-delayed event in the output of the demodulator. A second binary counter (Z') to which a reference frequency is applied can also latch itself by means of a logic circuit (V') when a certain count has been reached. However, it is only enabled by the input signal after the input signal has ended and is interconnected with the first binary counter (Z) in such a manner that it reenables the first counter (Z) with its own latching and resets the demodulator output. This results in an output signal which is time-delayed with respect to the input signal but has the same length. Advantages: selective signal detection, good noise characteristic, low-distortion signal processing; monolithically integrated digital receiver circuit. Main field of application: ultrasonic range finding in accordance with the echo method. <IMAGE>