发明名称 TEST CIRCUIT
摘要 PURPOSE:To decrease a memory capacity of a memory means storing information for the control of the operation of each circuit as well as to enable a test of the circuits which operate faster than the memory means reads out by freeing the memory means from storing information for the test. CONSTITUTION:A test of operating speed is made, not by feeding an instruction code from a memory means of a long access time such as a ROM but by feed ing an instruction code from a high speed pattern generator through external input terminals 17-1-17-10, decoding it by a decoder 16 to control each circuit and comparing the result with an expected value. In this way, a test can be made on the circuits which operate faster than an instruction ROM reads out.
申请公布号 JPS61193238(A) 申请公布日期 1986.08.27
申请号 JP19850031962 申请日期 1985.02.20
申请人 NEC CORP 发明人 ISHIKAWA YUTAKA
分类号 G06F11/22;G06F12/16;H01L21/66 主分类号 G06F11/22
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