| 摘要 |
PURPOSE: To increase integration density of cells by minimizing a cell area on a substrate by a method, wherein cell transistors are formed in a sidewall of a trench provided in the substrate forming a cell capacitor, and a word line and a bit line are mutually intersected in an upper part of the trench. CONSTITUTION: Transistors 18 of each memory cell 30 are of a bulk silicon structure having a polysilicon gate, and a channel 44 is a part of a P-epitaxial layer 34, and a source region 48 (a part of one pole plate of a capacitor 12) and a drain region 20 (a bit line 20) are N<+> -diffused substrates in the P-epitaxial layer 34, and a gate oxide layer 46 grows on a trench face of the P-epitaxial layer 34. Further, gates are a part of a word line 14 layer of polysilicon. An insulated oxide layer 42 has considerable thickness, and even so, the word line 14 gated is of a structure which overlaps the source and drain regions of transistors 18. Thereby, an electric charge storing area per unit area of the substrate is increased, and memory density can be maximized. |
