发明名称 |
Binary coded decimal number division apparatus |
摘要 |
In preparation of addresses of a quotient prediction table used in a binary coded decimal number division scheme with predetermined bits of a dividend and a divisor in binary coded decimal representation, the addresses are modified with the redundant bits. The absolute bit number for the addresses is thus decreased, whereby data quantity and hence capacity of RAM required for implementing the quotient prediction table can be significantly reduced, while satisfactory function of the quotient prediction table being assured. The apparatus for the binary coded decimal number division is implemented inexpensively in a small size.
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申请公布号 |
US4603397(A) |
申请公布日期 |
1986.07.29 |
申请号 |
US19830462423 |
申请日期 |
1983.01.31 |
申请人 |
HITACHI, LTD. |
发明人 |
OHTSUKI, TORU;OSHIMA, YOSHIO;ISHIKAWA, SAKO;FUKUTA, MASAHARU |
分类号 |
G06F7/491;G06F7/493;G06F7/496;G06F7/508;G06F7/52;(IPC1-7):G06F7/52 |
主分类号 |
G06F7/491 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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