发明名称 MEMORY ACCESS CONTROLLING SYSTEM
摘要 PURPOSE:To simplify the constitution of hardware by using a common buffer not only when data which has been read out of a main storage is transferred to a processing request origin, but also when it becomes address information which is brought to access to the main storage again. CONSTITUTION:Processing requests to a main storage device 30 sent from plural lower rank processing parts A, B and C are stored temporarily in ports 22A, 22B and 22C, selected by a selector 28 together with a repeated main storage access request from a selector 27, and processed successively. A main storage access requesting circuit MAD23 generates a main storage address in accordance with an access request, and set it to an address data register ADR24. Data which has been read out of the main storage 30 by this address is stored in a readout data register, and thereafter, divided into readout buffers RDB26A-26C by each separate access request origin. In case of the repeated access request, it is sent to the selector 28 through the selector 27.
申请公布号 JPS61165144(A) 申请公布日期 1986.07.25
申请号 JP19840269252 申请日期 1984.12.20
申请人 FUJITSU LTD 发明人 SEKINE MAKOTO;OKUYA SHIGEAKI
分类号 G06F12/02;G06F12/00 主分类号 G06F12/02
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