| 摘要 |
PURPOSE:To facilitate a testing by a method wherein an IC and a testing circuit are provided in a wafer, a signal is received by an outside device and the testing circuit, the signal is given to the IC, and the result of comparison of said signal and the output of the testing circuit is outputted to outside. CONSTITUTION:After each chip 1 is reset, a calculation 11 is performed by giving a clock signal 1 from outside, signals TI1-TIn and TO1-TOm having the content corresponding to a numerical value 1 are generated 12, and the signal s are given to each chip through a buffer 13. The signal i is inputted to terminals 1A1-1An, the signal is outputted from terminals 1B1-1Bm, it is compared with a signal TO by the EX-OR circuit 4B1-4Bn located in the region 4 outside the chip, and the result (0) is outputted by an OR circuit 4C when all signals are coincided with each other. The results TR1-TRk are read into FR1-FRk from k-pieces of chips in synchronization with the (1) of a clock signal 2 through the AND circuit CA1 of each stage of resistor 14. The memory is shifted stage by stage by the (1) of the clock signal 2, it is read out successively from a pad 49, and a defective or non-defective judgement is given. A wafer can be tested by merely connecting to the outside device using pads 49-54, and the shifting of the wafer and a probe are unnecessitated. |
