| 摘要 |
PURPOSE:To simplify the constitution of a title device by reading out the value of a counter as an address and latching it with respect to a random storing circuit which an execute read-out and write at a prescribed period, writing the output of an input use latching circuit to its address, and making a counter step. CONSTITUTION:The address bus of a random storing circuit 2 is connected to a counter circuit 1 whose count number is smaller by '1' than the number of necessary delay steps, its data bus is connected to the output of a three-state circuit 4 and the input of an output use FF circuit 5, and the circuit 4 is connected to an input use FF circuit 3. In this state, for instance, when the circuit 1 is a ternary counter, a data inputted by the circuit 3 is sent to the circuit 2 through the circuit 4, written to an address '0' indicated by the circuit 1, it is set as the next address by making the circuit 2 step, and after the same operation is repeated three times, the output of the circuit 2 is inputted to the circuit 5 by the rise of the next clock pulse. |
