发明名称 FAST FOURIER TRANSFORM CONTROL SYSTEM
摘要 <p>PURPOSE:To eliminate the need for loading an address index list and to speed up operation by producing successively the address indexes based on the counter value output of a counter circuit and controlling the output array of butterfly operations by those address indexes. CONSTITUTION:The vector data to be calculated is transferred to a vector register 21 from a memory 20, and a prescribed arithmetic is carried out by an arithmetic mechanism 22. The data on the result of said arithmetic is held by the register 21 and then processed by the mechanism 22 or transferred to the memory 20. An address generating circuit 25 produces automatically an address index list based on the count value output of a counter circuit and sets it to an address index register 23. The register 23 controls an array of arithmetic outputs.</p>
申请公布号 JPS60254276(A) 申请公布日期 1985.12.14
申请号 JP19840109944 申请日期 1984.05.30
申请人 FUJITSU KK 发明人 MIURA KENICHI
分类号 G06F17/14;(IPC1-7):G06F15/332 主分类号 G06F17/14
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