发明名称 SIGNAL FORMING CIRCUIT
摘要 PURPOSE:To improve the frequency accuracy, to reduce power consumption and to attain cost-down of a tone generator by providing a correction circuit retarding the count operation of a frequency circuit of original oscillation comprising a frequency dividing counter and using the correcton circuit to give a signal retarding the count with a proper interval to the frequency divider circuit. CONSTITUTION:When n-set of reset signals RS1 having a frequency being 1/m frequency division of an original oscillation signal phi0 outputted from a frequency divider counter 21 enter a counter 11 in a correction circuit 10, a reset circuit 12 resets the counter 11 and the counter 21 is reset again with a delay of one clock than the reset signals RS1. As a result, an output signal RS1 of the reset circuit 22 fed to a Jonson counter (4) is subjected to extended pulse width by (m+1) times once per n-time, whose pulse width has been m-time thatof the original oscillating signal phi0. That is, the frequency dividing ratio is m+(1/n) and the original oscillating signal phi0 is frequency divided by the frequency dividing ratio in fractional expression.
申请公布号 JPS61144902(A) 申请公布日期 1986.07.02
申请号 JP19840266172 申请日期 1984.12.19
申请人 HITACHI LTD 发明人 KANDA SHINYA
分类号 G10K15/04;H03B28/00;H04M1/50;H04Q1/45 主分类号 G10K15/04
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