| 摘要 |
PURPOSE:To constitute flexibly a high-speed multi-processor system by connecting mutually optionally same unit processing devices. CONSTITUTION:In case of the master mode output and slave mode input, a selected address is outputted from the master mode output side to an address bus. An input control circuit of each slave each slave mode input connected to the address bus detects the coincidence between each own address and the selected address, the input control circuit subjected to coincidence checks the state of an input data queue and when it is possible to receive data, data transmission is requested to the master mode output via a control bus and the data is fetched to the input data queue. In case of the slave mode output and the master mode input, the selection address is outputted to the address bus from the master mode input side. An output control circuit of each slave mode output side connected to the address bus detects the coincidence between each own address and the selection address, the coincident output control circuit checks the state of the output data queue and when it is possible to transmit data, the data is transmitted. |
