A SEMICONDUCTOR MEMORY DEVICE HAVING A MEMORY MATRIX AREA AND A PLURALITY OF PERIPHERAL CIRCUITS

摘要

The device has a memory cell matrix area in which memory cells are provided at intersections of bit lines (Bn, Bn min , Bn+1, Bn+1, Bn+1 min ) and word lines (WD). Peripheral circuits, for example, sense amplifiers (SAn, SAn+ 1), are provided in peripheral circuit blocks (SA) and are connected to bit line pairs (Bn, Bn min ; Bn+1, Bn+1 min ). The width of the sense amplifiers (SAn, SAn+ 1) corresponds to the distance between bit lines Bn and Bn+1 min . Sense amplifiers SAn and San + 1 connected to line pairs Bn, Bn min and Bn+ 1, Bn+ 1 min are arranged below another in the direction of the bit lines. All the sense amplifiers are arranged in two ranks (blocks SA, SA) so that the need to fan out the bit lines to a sense amplifier block is avoided.