| 摘要 |
PURPOSE:To perform the logical simulation of a large-scale circuit including MOS elements precisely at a high speed by providing four partial processes, i.e. 1) registration and read, 2) element input side read, 3) decision, and 4) element output side read and circulating data in the order of 1, 2, 3, 4, 1-. CONSTITUTION:The whole device consists of three loops. The 1st (the 2nd or the 3rd) loop 17 (18, 19) consists of a registering and reading device 1 (2,3) which registers and reads an activated element, an element input side reading device 4 (5, 6) which reads the kind of the element and the state of an input pin, a decision device 7 (8, 9) which performs the logical operation of the element and decides whether the output state changes or not, a data buffer 10 (11, 12) having an FiFO function, an output side reading device 13 (14, 15) which reads the output destination element of this element and a delay time, and a switching network 16. Consequently, the parallelism in a problem is extracted at a maximum to make calculations, so the operation is speeded up. |
