| 摘要 |
PURPOSE:To fetch an asynchronous reception data with high accuracy by using a variable voltage applied from an external terminal for an operation voltage of inverter circuits connected in cascade receiving a reference clock signal and forming its delay signal, adjusting the delay time and selecting a signal suitable for a digital signal applied asynchronously. CONSTITUTION:A reference clock signal phi0 becomes a clock signal phi1 delayed through one set of inverter circuits. The clock signal phi1 becomes a clock signal phi2 through one set of similar inverter circuits. Further, similarly clock signals phi3-phi8 delayed sequentially by a delay time of one set of the inverter circuits are formed. In changing an operating voltage VS of the inverter circuits, the delay time of the inverter circuits is adjusted to form an optimum sampling clock signal in response to the reception condition. |
