| 摘要 |
PURPOSE:To improve processing capability by establishing circuits for memory, I/O decode, wait adjustment and wait selection, and by selecting effectively the wait number of CPU against access of memory and I/O device. CONSTITUTION:A wait adjustment circuit has terminals W1-S3, and O1-O3, and in case of normal clock speed, it selects W1, and directly sends and uses a control signal CNT from CPU to a wait generation circuit 5. When the basic clock of the CPU1 becomes rapid and it is necessary to increase the number of wait, it selects terminals O2 and W2, or O3 and W3. When these are selected, the number of wait is increased by 1 or 2 comparing with the W1. Namely, W2 delays by one clock by DFF41, and W3 delays by 2 clocks by DFF 41, 42. Thus, it is possible to vary the wait number of system by delaying control signals CNT from the CPU1 according to the change of the basic clock CLK of CPU1. |
