Auto-zero sample and hold circuit.

摘要

A sample and hold circuit contains a pair of differential amplifiers (A1 and A2) switchably arranged in series. The circuit input signal (VIN) during sample is provided to the first amplifier (A1) which is coupled to a storage capacitor (C). The second amplifier (A2) provides the circuit output signal (VOUT) during hold. Switching circuitry (S1, S2 and S3) enables the input and output signals to undergo the same transfer function in the first amplifier. The voltage offset of the first amplifier is thereby cancelled out of the output signal, while the effect of the voltage offset of the second amplifier is reduced drastically so as to provide excellent auto-zeroing.