Circuit arrangement for a control memory operating on the queuing principle (FIFO memory)

摘要

The FIFO memory comprises a normal shift register (S-REG), to which the items of information to be stored (SEL-AD(REQ)) are fed via the first stage. The outputs of the register stages are connected one after the other to the inputs of a selector switch (MUX), which receives the items of selection control information in binary-coded form from a binary forward/backward counter (CNT), which upon each request (REQ) counts forwards one increment and upon each relaying request (RESP) counts backwards one increment, so that the selector switch (MUX) in each case switches through the oldest, not yet relayed information in the shift register (S-REG) to the output. <IMAGE>