| 摘要 |
For a maximum of 2<n> memory banks, a corresponding number of control/permutation logic circuits (SVL-A,...H) is provided which in each case consists of a comparator circuit (COMPi) and a selection circuit. In the comparator circuit, the old priority (Pi) supplied to first n inputs is compared with the hit priority (PHIT) supplied to second n inputs, in such a manner that, with a hit priority which is equal or higher or lower in comparison with the old priority, either the most significant new priority or a new priority which is lower by one priority step compared with the old priority or a new priority which is unchanged compared with the old priority (PN-A...,PN-H) occurs at the output of the selection circuit in dependence on the result of the comparator circuit, which new priority is stored as such in an associated priority memory (PS-A...PS-H). <IMAGE>
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