| 摘要 |
PURPOSE:To relieve the load of a decoding processing at a CPU and to improve the processing efficiency by fetching a serial data modulated by the length of a signal as a parallel data while being decoded automatically. CONSTITUTION:In observing a serial data, when a point returned timewise by 5T'/2 from the trailing of each pulse falling down from H to L is at H level, then the level is taken as logical ''1'' and when L, it is taken as logical ''0'', then a preceding data from a data including a trailing pulse corresponds well to a digitally processed data. Then a shift register 50 is triggered at the trailing of each pulse of the serial data itself modulated by the length of the signal and the data at a point of time going back by 5T'/2 from the point of time is fetched, then the signal is decoded automatically. Then the decoded data is stored in the shift register 50 and fetched to a CPU51 as a parallel data.
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