发明名称 VARIABLE GAIN AMPLIFIER CIRCUIT
摘要 PURPOSE:To decrease the equalization deviation to a change in the length of line by using an AGC loop making the peak value constant and an automatic gain control loop of f<1/2> characteristics. CONSTITUTION:A signal inputted to an input terminal 11 is fed to a peak value AGC loop comprising a peak value detector 16, an AGC control circuit 17 and an AGC amplifier 12 having a flat characteristic. The closed loop is activated so that a peak value of an output signal after equalization at an output terminal 15 is constant and executes equalization amplification to a term Bl in line loss ( Af<1/2>+B)l, where A, B are constants, (f) is a frequency and (l) is a length of transmission line. Further, said input signal is fed to a closed loop comprising a pulse width detector 18, an AGC control circuit 19 and an AGC amplifier 13. The closed loop controls the gain so that the pulse width of the output signal after equalization at the output terminal 15 is constant and the equalized amplification to the term Af<1/2>l of said formula is attained.
申请公布号 JPS60251710(A) 申请公布日期 1985.12.12
申请号 JP19840107403 申请日期 1984.05.29
申请人 FUJITSU KK 发明人 MIYAKI YUUJI;ARAI MASANORI;ENDOU TAKEMI
分类号 H03G3/20;H03H11/04 主分类号 H03G3/20
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