| 摘要 |
PURPOSE:To detect effectively speed even at a super-low speed, by measuring number Cn of pulses of a high-frequency clock until detection of the No.2<n> pulse of a shaft encoder and searching for K/C (K: proportional constant determined number of clocks at the full speed and number of pulses) basing upon this number Cn of pulses. CONSTITUTION:A shaft encoder 1 generates a pulse signal EAB of a plurality of phase A, B. This signal EAB is supplied to a judging circuit 13 of rotating direction of pulse sending a pulse signal E synchronized corresponding to a plural multiplication (for example 4 times) of a detecting pulse basing upon the clock pulse C. This signal E is counted by the No.2<n> pulse detecting counter circuit 14 and only No.2<i> (i=0, 1...n) pulse is selected and detected. Further, number Cn of pulses of the clock until detection of the No.2<n> pulse of the encoder 1 is measured by a circuit consisting of clock-counter circuit 3, latch circuit 8, etc.. K/C is detected 10, basing upon this number of pulses Cn, by a instruction of a microprocessor circuit 2 and the speed is detected by shifting it in the lefthand direction by an exponent number n. |
