发明名称
摘要 <p>PURPOSE:To enable the overlap writing of the data with just supply of the new data into the memory by giving a control under which only the data in the prescribed state is written among those to be supplied to the memory element. CONSTITUTION:The parallel data of plural bits are supplied to memory elements 21-1-21-n from data lines 22-1-22-n, and this bit data is supplied to the WE terminal of each memory element via inverters 23-1-23-n. Each memory elememt becomes the writable state only when ''0'' is applied to the WE terminal. Thus, the data is rewritten only for the memory element which received application of input data ''1'', and the original data is stored as before for the memory element to which input data ''0'' was supplied. Thus, the new data of ''1'' can be written in overlap with no erasion of the original ''1'' data, omitting the complicated process.</p>
申请公布号 JPS6051748(B2) 申请公布日期 1985.11.15
申请号 JP19780049852 申请日期 1978.04.28
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 TAKEUCHI HISAHARU;IMAMURA MAKOTO
分类号 G06F12/04;G06F12/06;G06T3/00;G11C7/00 主分类号 G06F12/04
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