| 摘要 |
PURPOSE:To implement the junction depth of 0.1mum or less of a source and drain junction even for a P-channel MIS type FET, by forming at least a part of a source and drain region by the ion implantation of indium or potassium. CONSTITUTION:A thick oxide film 102 for isolating elements is grown on the surface of a semiconductor substrate 101 by a selective oxidation method. After a gate insulating film 103 is grown, a polycrystal silicon layer 104 is grown on the insulating film 103 in a overlapped manner. Then a photoresist film 105 is applied and gate patterning is performed. With the photoresist as a mask, the polycrystal silicon layer 104 and the oxide film 103 are etched in this order, and a gate 10 is formed. With the gate 106 as a mask, indium ions are implanted, and an indium implanted layer 107 is formed. Then light of a halogen lamp, whose output results in the substrate temperature of about 1,000 deg.C, is projected, and the indium implanted layer is made active. |
