| 摘要 |
PURPOSE:To obtain the titled modulator suitable for circuit integration by bringing a clock frequency to 1/2<2/3> for the same noise level with less number of added elements and constituting a signal coder with simple structure. CONSTITUTION:A voltage signal inputted from a signal input terminal 11 is impressed to an adder 12 in a form of a charge by a means 18 converted into a charge proportional to the voltage signal. When an output of an integration device 13 exceeds 1/2Vp succeedingly, a vharge corresponding to a -Vp is fed to the adder, and when the output reaches -1/2Vp or below, a charge corresponding to a +Vp is fed to the adder. Only the input signal is fed to the integration device when the output is -1/2Vp. Then the feedback loop is operated so that the output of the integration device does not exceed + or -1/2Vp. Since the value is + or -Vp in a conventional circuit, it is expected that thenoise voltage of the converted output is decreased to 1/2. It is known in the noise voltage per unit band width of a delta sigma modulator that it is proportional to fc<3/2> when the maximum input voltage is constant, where fc is the sampling frequency. Thus, the clock frequency is decreased to 1/2<2/3> to obtain the same noise level by using the device of this invention. |
