| 摘要 |
PURPOSE:To eliminate the need to cut off the supply of power when a memory cassette is loaded and unloaded by connecting a pull-up resistance to a chip enable signal line as well as to a write signal line respectively. CONSTITUTION:A CPU5 has no malfunction even in case a memory cassette 3A is loaded to and unloaded from a processing part 4A during application of a power supply owing to the connection of a resistance RD. If the connection is incomplete between the cassette 3A and the part 4A, a chip selection circuit 8 transmits a chip enable signal to a line l7 by an instruction given from the CPU5 in order to actuate a ROM6. Under such conditions, no short circuit is produced even in case a memory 3a of the cassette 3A transmits a data signal of a low level by mistake in a state where the CPU5 transmits the data signal of a high level among those data signals stored previously in the ROM6 since the resistance RD is connected to a data bus l6. |
