| 摘要 |
PURPOSE:To perform control without any disorder of a pipeline and to improve the processing ability of instruction execution control by by-passing register write data in case of major part of register interference. CONSTITUTION:When a leading instruction (a) is a low-address instruction or load register instruction, etc., a following instruction (c) is not interlocked under by-pass control as shown in a time chart in a figure even if a result storage register address as the 1st operand of the leading instruction (a) and a register address used for the address calculation of the 2nd operand of the following instruction (c) coincide with each other. When arithmetic is performed at the stage A of the instruction (a) by using a circuit for address calculation, data on the calculation result is by-passed from a by-pass register for the address calculation of the instruction (c) to calculate the operand address of the instruction (c).
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