Sampling frequency conversion device

摘要

An input digital signal with M(=5) samples/second is converted to an output signal with N(=6) samples/second with n(=9) quantization bits. The device comprises parallel shift registers each having bit length P+n(P=11) for accepting an input signal with bit length n; an address converter for providing the continuous P bits in input signals from each of said parallel shift registers for every shift operation of said shift registers; N groups of ROMs (read only memory) storing the predetermined value in each address which is designated by output of said address converter; a shift register adder for accumulating output of said ROMs with shift operation; and an output gate coupled with output of said shift register adder for providing a converted output signal.