| 摘要 |
PURPOSE:To decrease the through-current at precharge by retarding a load transistor (TR) of the final stage of a delay state comprising two stages of inverters than the leading of the other input. CONSTITUTION:The level of an input node FIN is at a low level at the precharge period and when input nodes FP1, FP2 both rise, since TRs Q2, Q7 are turned on, and a gate potential of TRs Q4, Q8, Q10 goes to a low level. As a result, the TRs Q4, Q8, Q10 are turned off. Then the input node FP3 rises and the TRQ3 is turned on, then no through-current flows to the inverter constituting the delay stage. After the TRQ3 is turned on, TRs Q9, Q11 are turned on, then no through-current flows to a waveform shaping stage 2 and an output buffer stage 3. |
