发明名称 INTERRUPTION PROCESSING CIRCUIT TO CPU
摘要 <p>PURPOSE:To guarantee accurate operation of a CPU by using a monostable multivibrator to inhibit an unmasked interruption applied to the CPU for a prescribed time at application power. CONSTITUTION:When power failure is restored by the application of power, an unmasked interruption NMI release signal is generated to actuate a monostable multivibrator 5. Thus, an output terminal O2 of the vibrator 5 goes to a low level for a prescribed time to inhibit the input of the NMI to the CPU1 for a prescribed time. The CPU1 processes power failure restoration such as return of stack pointer and return of register and is restored. Thus, when an RAM backed up by a battery is used for the memory, even if power is applied, the movement of the software is brought into the continuous movement.</p>
申请公布号 JPS60124734(A) 申请公布日期 1985.07.03
申请号 JP19830233947 申请日期 1983.12.12
申请人 TOKYO DENKI KK 发明人 SUZUKI HISAO
分类号 G06F9/48;G06F1/00;G06F1/30;G06F9/46 主分类号 G06F9/48
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