| 摘要 |
PURPOSE:To attain high speed data transfer not by the hand shake system by forming a ready signal with a clock pulse outputted together with a data and a read signal to read the data. CONSTITUTION:A data D1 is started for transmission to a data bus of a CPU1 by a buffer gate 8 at a time t1. After the time T is elapsed from the time t1, when the CPU1 completes the reading of data of the data bus, a data read signal IOR is relinquished and an output (b) of a gate circuit 3 goes to a high level (at time t2). Then a D flip-flop 6 is reset, a ready signal IORDY is relinquished and an output of the buffer 8 is made ineffective. When the output (b) of the gate circuit 4 is at a high level at the falling of a clock DCK' (at time t4), no change occurs but an output (c) of an AND gate 7 goes to a high level at the falling of the output (b) of the gate circuit 4, the flip-flop 6 is set and the ready signal IORDY is generated. |
