A single mask process for implanting self-aligned source and drain electrodes to form a cmos structure.

摘要

A process for forming self-aligned complementary n* and p+ source/drain regions in CMOS structures uses a single mask to form both the n- channel implant and then the p+ channel implant. The mask comprises a resist pattern (20, Fig. 3) which covers the p+ channel region while the n+ source and drain regions (24, 26) are ion implanted. The resist mask is then used as a lift-off mask in order to cover the n+ channel region while the p+ source and drain regions (32, 34) are ion implanted.