METHOD FOR PARTITIONING MAINFRAME INSTRUCTION SETS TO IMPLEMENT MICROPROCESSOR BASED EMULATION THEREOF

摘要

METHODS FOR PARTITIONING MAINFRAME INSTRUCTION SETS TO IMPLEMENT MICROPROCESSOR BASED EMULATION THEREOF Methods of applying LSI and microprocessors to the design of microprocessor-based LSI implementation of mainframe processors are described. The mainframe instruction set is partitioned into two or more subsets, each of which can be implemented by a microprocessor having special on-chip microcode or by a standard off-the-shelf microprocessor running programs written for that purpose. Alternatively, one or more of the subsets can be implemented by a single microprocessor. In addition, a subset of the partitioned instruction set can be implemented by emulating software, by off chip vertical or horizontal microcode, or by primitives. But, however partitioning is implemented, the end result thereof is to keep the critical flow paths, associated with the most frequently used instruction subset, as short as possible by constraining them to a single chip.