| 摘要 |
PURPOSE:To eliminate the use of an overflow detecting circuit and to simplify the timing control for division by performing a division operation through the normalization of a divided and the addition of two compliment values of a dividend and a divisor. CONSTITUTION:A dividend and a complement of 2 of a divisor are fed to a dividend register 31 and a divisor register 32 respectively to be normalized there. Then a quotient register 33 is cleared and the loop frequency is set to a loop counter 36. The value of the register 32 is shifted by arithmetic to the right to be 1/2-multiplied. The value of the register 31 is added to that of the register 32 and supplied to the register 31. Then 1 is added to the value of the register 33. Both registers 31 and 33 are simultaneously shifted left until the value of the register 31 is normalized. In this case, the setting frequency of the counter 36 is reduced for each shift of both registers. Then said addition and normalization are carried out until the above-mentioned setting frequency is set at 0. As a result, both of a quotient and the residual are set to registers 33 and 31 respectively. |
