| 摘要 |
<p>Arranged between a first and a second common terminal (5 and 6), the circuit comprises a first circuit formed by the series arrangement of a first PNP-transistor (T,) and a second NPN-transistor (T2), and a second circuit formed by the series arrangement of a third PNP-transistor (T3), a fourth NPN-transistor (T.) and a first resistor (R,). The commonned bases of the second and fourth transistors (T2 and T.) are driven by a first differential amplifier (3), whose non-inverting input is coupled to the collector of the second transistor (T2) and whose inverting input is coupled to a tap (7) of a voltage divider (R2, R3) formed by a second and a third resistor. The commonned bases of the first and third transistors (T, and T3) are driven by a second differential amplifier (4), whose non-inverting input is coupled to the collector of the third transistor (T3) and inverting input to the tap (7) of the voltage divider (R2, R3). Because of the drive by means of the first and second amplifiers (3 and 4). the collector-base voltages of the first and third transistors (T2 and T3) and of the second and fourth transistors (T2 and T.) vary to an equal extent in the event of supply voltage variations, as a consequence of which the symmetry of the circuit is preserved</p> |
