| 摘要 |
PURPOSE:To attain ease of large scale circuit integration by adding a data transmission/reception function in the circuit so as to transmit and receive data with a multiplex line and also forming the required operation timing from an externally designated condition and a basic clock. CONSTITUTION:The data is received in the timing LTO from a multiplex data on a signal line 7A-1 by a register 11. Speed converting circuits 12-1-12-4 fetch the data in the register 11 in the timings of LT1-LT4 and circulate the fetched data in the transfer speed of a bus 4a. Tri-state elements 13-1-13-4 switch a gate in the timings of OP1-OP4 respectively and transmit the data to a specific time slot location on the bus 4a. A line state detecting circuti 14 forms a status signal by taking the data in the register 11 as a reference and transmits the data onto a bus 4b via a speed converting circuit 15-i and a tri-state element 16-i. The timing forming circuit 21 forms the timings LT1-LT4 and an OP5 according to information PHN, BRT designated externally, OP1-OP4 by BRT and TSN and forms LT5 from the three sets of information.
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