发明名称 ASYNCHRONISM DETECTING SYSTEM
摘要 PURPOSE:To detect the asynchronism of a PLL circuit with small-scale circuit constitution by providing a voltage discriminating device identifying an asynchronous voltage and a memory storing this discriminated output to an output of a phase difference detector of a phase locked loop. CONSTITUTION:When the input to the PLL circuit is interrupted and the circuit becomes asynchronous state, an output of a phase difference detector PD2 goes to an upper limit voltage VH or a lower limit voltage VL, an output frequency of the PLL circuit becomes respectively an fH or over or an fL or below representing out of synchronism. When the asynchronous state is reached because of a failure in the phase synchronizing loop of the PLL circuit, an output of a PD2 is oscillated in a beat frequency of two frequencies inputted to the PD2 between the voltages VH and VL via a 1/n frequency divider 1 and a 1/m frequency divider 5. The voltage discriminator 7 identifying that the output voltage of the PD2 goes to the voltage VH or VL is provided and if an output of the discriminator 7 becomes an output representing the asynchronous state even once, this output is stored in a memory 8 and the asynchronous state is detected by this stored content.
申请公布号 JPS59219026(A) 申请公布日期 1984.12.10
申请号 JP19830093530 申请日期 1983.05.27
申请人 FUJITSU KK 发明人 NAKAJIMA YOSHIBUMI;HASHI TOSHIO;CHIBA KAZUHARU
分类号 H03L7/095 主分类号 H03L7/095
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