发明名称 PREFETCH CONTROL SYSTEM OF INSTRUCTION
摘要 PURPOSE:To improve the fit factor of estimation and to increase the executing speed of an instruction by turning on or off an instruction prefetch control register with the instruction. CONSTITUTION:An instruction is set to an instruction register 1 in the 2nd machine cycle, and this instruction is equal to an unconditional branch instruction. As a result, the output 15 of a test matrix 9 is turned on with the output of an OR gate 21 turns on. Then a selector 5 selects a signal line 12 through which as instruction branch destination adderss B of a register 1, and the address B of the next instruction is set to an address register 2. The next instruction is equal to a conditional branch instruction and has high probability for success, and therefore an instruction prefetch control register 7 is set by an instruction. In such a way, a program producer judges the probability for branch success of a conditional branch instruction and turns on and off the register with an instruction. Thus it is possible to improve the hit factor for estimation of the instruction address to be executed next.
申请公布号 JPS59183434(A) 申请公布日期 1984.10.18
申请号 JP19830057032 申请日期 1983.04.01
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 TAJIMA SEIJIROU;HIRANO MASANORI
分类号 G06F9/38 主分类号 G06F9/38
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