发明名称 |
MULTIPLEX TRANSMISSION SYSTEM |
摘要 |
PURPOSE:To attain the effective use of a circuit by fetching the start-stop synchronous data for each character and allotting the time slot of a high-speed circuit when necessary. CONSTITUTION:The start-stop synchronous data supplied from low-speed circuits 11-1N are fetched by transmission/reception parts 21-2N. Then the start/stop bit is excluded and the data part equivalent to one character is supplied to a circuit number providing part 3. The numbers corresponding to circuits 11-1N are provided and stored in a transmission buffer 4. A high-speed data transmission/reception part 5 extracts the character data with circuit number out of the buffer 4 and transmits it to the time slot of a high-speed circuit 6. Then the part 5 receives the character data with circuit number from the circuit 6 in accordance with the time slot, and a circuit number identifying part 7 identifies the circuit number and distributes the character data to reception buffers 81- 8N. The parts 21-2N extract the reception data out of buffers 81-8N and provide the start-stop bits to the reception data. These data are received by terminals through circuits 11-1N. |
申请公布号 |
JPS59133754(A) |
申请公布日期 |
1984.08.01 |
申请号 |
JP19830006710 |
申请日期 |
1983.01.20 |
申请人 |
NIPPON DENSHIN DENWA KOSHA |
发明人 |
KAWANO SHIGEKAZU;NOGUCHI SEIICHI;INOUE MASAYOSHI |
分类号 |
H04J3/00;H04L5/22;H04L5/24 |
主分类号 |
H04J3/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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