发明名称 DUAL TYPE OPERATION PROCESSING DEVICE
摘要 <p>PURPOSE:To detect accurately the synchronization between a master side and a slave side, by converting a master-side synchronizing signal to a serial signal and converting it to a parallel signal again by two series synchronization control circuit which are provided between master-side and slave-side operation processing circuits. CONSTITUTION:Operation processing circuits 1 and 2 transmit and receive data to and from various circuits and devices, which are not shown in Fig. through a data bus to control these circuits and devices and are connected to a high-speed data bus 8 through high-speed bus control circuits 6 and 7 to constitute a dual type. When the synchronizing signal appears in the master-side operation processing circuit 1, it is converted to a serial signal in a synchronization control circuit 4 and is inputted to the operation processing circuit 4 through an input/ output port part 5 and is converted to a parallel signal again and is inputted to the slave-side operation processing circuit 2 and is compared with the synchronizing signal generated on the slave side, and the state of synchronization is transmitted to the master side through synchronization control circuits 4 and 3. Thus, the synchronous state is accurately detected with a simple constitution.</p>
申请公布号 JPS59132059(A) 申请公布日期 1984.07.30
申请号 JP19830006214 申请日期 1983.01.17
申请人 MATSUSHITA DENKI SANGYO KK 发明人 SATOU MITSUO;KIMOTO ITSUOKI
分类号 G06F15/16;G06F15/17;G06F15/177 主分类号 G06F15/16
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