发明名称 CLOCK COMPARATOR CONTROL SYSTEM
摘要 PURPOSE:To prevent the interruption of a comparator from being ceased even if the value of a clock comparator register varies during scanning operation by confirming and setting, etc. the contents of a TOD (Time of DAY) timer and a clock comparator register by a coincidence circuit. CONSTITUTION:This system performs data processing by using a scan loop system and the coincidence circuit 3 compares the contents of the TOD timer 1 with the contents of the clock comparator register 2 wherein a desired value is set by the instruction of the timer; when they coincide with each other, an FF4 is set to start a microprogram. Further, a scan control circuit 5 which scans the register 3 and another register 6, etc., is provided, and the FF4 is set when its scanning operation is completed to start a microprogram interruption.
申请公布号 JPS59125420(A) 申请公布日期 1984.07.19
申请号 JP19820234069 申请日期 1982.12.30
申请人 FUJITSU KK 发明人 MIYAJIMA SHIGERU;HAMAOKA SHIYOUSUKE
分类号 G06F1/14;G06F9/48;G06F11/22 主分类号 G06F1/14
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