| 摘要 |
PURPOSE:To realize quantitative control and to ensure an assured operation with no effect given by component elements, by taking an input control signal temporarily into a buffer circuit and then delivering a selecting signal with a limited timing phase. CONSTITUTION:The L level is transferred synchronously with an output signal 16 for both positive and negative selecting signals 28 and 29 which are equal to the output of a buffer circuit 21 when no positive nor negative signal exists. As a result, an output signal 23 of a selecting circuit 19 selects a reference phase signal 30 and latches 20 it to supply it as a clear signal of a shift register circuit 18. Thus a signal 16 of 3T0 is generated to a basic frequency signal period T0. When a positive signal 14 is generated, the H level is transferred for the signal 28. Then the signal 23 selects a positive compensated phase signal 31 and then supplies a clear signal to the circuit 21 via the circuit 18 and a clear circuit 26. As a result, the signal 16 has a period 4T0. Then a negative signal 15 is generated, and the L level is transferred for the signal 29. The signal 23 produces a negative compensated phase signal 32. As a result, the signal 16 has a period 2T0. |
