| 摘要 |
PURPOSE:To save power consumption and improve reliability of LSI for fluctuation of power supply by providing a bias cell SBC which generates one reference voltage to a plurality of gate cells and supplying a power to each logic gate through bias buffer circuits. CONSTITUTION:The cell EXC for junction with external circuits, bias cell SBC for generating the reference voltage and cell INC in internal logic circuits are sequentially arranged on a chip CHP. An INC comprises a bias buffer INB, the reference voltage sent from the one SBC is supplied to a plurality of INB's and is input to each logic gate circuit. On the other hand, the reference voltage is supplied to an EXC as a bias voltage. Power consumption can be reduced by supplying a voltage to all gates on the chip from the one bias circuit as explained above and the reference level which does not cause mis-operation with fluctuation of power source voltage ca be supplied to the master slice LSI of emitter junction logic. |
