发明名称 MULTIACCESSIBLE MEMORY SYSTEM
摘要 PURPOSE:To shift the right to use a memory on every access operation and to utilize the memory effectively by inputting an access control signal directly to a control circuit and carrying out switching every time word access unit is attained. CONSTITUTION:An arithmetic processor 1A when reading data out of a memory device 4 inputs the access control signal CTRL#A of a signal READ to a control circuit 3. The control circuit 3 sends back an acknowledge signal ACK#A if the output Q of a flip-flop 13 is (1). Switches 5, 6, and 7 are driven through a selection signal line 20A to connect a control signal line 16A, address signal line 18A, and data signal line 19A to the memory device 4. The calculating processor 1A once reading data stops sending the control signal CTRL#A and the transmission of the acknoweldge signal ACK#A is stopped.
申请公布号 JPS593665(A) 申请公布日期 1984.01.10
申请号 JP19820113307 申请日期 1982.06.30
申请人 FUJITSU KK 发明人 NAKADA RIYOUICHI
分类号 G06F12/00;G06F9/52;G06F13/16;G06F15/16;G06F15/167;G06F15/177 主分类号 G06F12/00
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